This invention relates generally to "power-on detect" circuits, sometimes referred to simply as "power detect", "power-on reset", "power enable" or "voltage detect" circuits. These circuits generally provide a power-on signal that indicates when the voltage level of a power supply voltage source has attained a predetermined acceptable level. More particularly, the present invention relates to a power-on detect circuit well suited for low voltage power supply operation less than or equal to 3.3 volts, and including a suppression circuit for eliminating false power-on signal indications.
Referring now to FIG. 1, a block diagram of a prior art power-on detect circuit 10 is shown including a resistor divider 12, a bandgap reference circuit 20, and a differential amplifier or comparator 24. Resistor divider 12 includes resistors 14 and 16. A first node 13 of resistor divider 12 is typically coupled to the VDD power supply voltage source, and a second node 17 of resistor divider 12 is typically coupled to ground. Resistors 14 and 16 are ratioed so that the output voltage, ROUT, on center tap 18 is equal to the VREF reference voltage on line 22 of bandgap reference circuit 20 when the VDD power supply voltage has attained the desired level. The ROUT voltage and the VREF reference voltage are compared by comparator 24. Once the ROUT voltage has exceeded the VREF reference voltage, a power-on signal PWREN is provided at the output of comparator 24 on node 26. The PWR signal indicates that the power supply voltage is in the acceptable range, and can be used to control various functions on, for example, an integrated circuit.
In FIG. 2, the ideal ROUT, VREF, and VDD voltages corresponding to the same labeled voltages shown in FIG. 1 are plotted against time. Initially, all three voltages are zero. As the power supply voltage is increased, the VDD power supply voltage and the VREF reference voltage rise together. The ROUT center tap voltage also rises, but at a linear ratio of the VDD and VREF voltages. At some point, typically about 1.1 volts for a bandgap reference voltage, the VDD and VREF voltages diverge. The VDD power supply voltage and the ROUT center tap voltage continue to increase, whereas the VREF reference voltage remains constant. At time t1, the ROUT and VREF voltages are equal, which corresponds in FIG. 2 to a power supply voltage of about 2.5 volts. Shortly after time t1, a valid PWREN power-on signal is generated.
In FIG. 3, the non-ideal ROUT, VREF, and VDD voltages corresponding to the same labeled voltages shown in FIG. 1 are plotted against time. In particular, the "non-ideal" or actual VREF voltage waveform for a typical bandgap circuit is dramatically different than the idealized version. As in FIG. 2, initially all three voltages are zero. As the power supply voltage is increased, the VDD power supply voltage, the ROUT center tap voltage, and the VREF reference voltage all rise at different rates. Notably, the VREF voltage rises at a rate slower than the ROUT voltage waveform, at least initially. At time t0, the VREF reference voltage quickly rises to its final value, typically about 1.1 volts. As the VREF voltage rises to its final value, it crosses the ROUT voltage. An undesirable false power-on signal indication can be produced at anytime prior to time t0. If a false power-on signal indication is generated, it will correspond to a VDD voltage significantly less than the desired minimum VDD voltage.
At low VDD supply voltages, a false power-on signal indication cannot be tolerated due to the extremely low power supply margin voltages. For example, if a 2.5 volt minimum VDD level is set for a valid power-on signal indication (which would correspond to a nominal three or 3.3 volt VDD power supply level), a voltage difference of as little as one hundred millivolts, i.e. a 2.4 volt supply voltage is unacceptable.
What is desired, therefore, is a power-n detect circuit that is compatible with low voltage operation and will not provide false power-on detect signals corresponding to an unacceptably low power supply voltage.